The SDR transceiver consists of two SDR receivers and of two SDR transmitters.
The implementation of the SDR receivers is quite straightforward:
An antenna is connected to one of the high-impedance analog inputs.The on-board ADC (125 MS/s sampling frequency, 14-bit resolution) digitizes the RF signal from the antenna.The data coming from the ADC is processed by a in-phase/quadrature (I/Q) digital down-converter (DDC) running on the Red Pitaya’s FPGA.
The SDR receiver is described in more details at this link.
The SDR transmitters consist of the similar blocks but arranged in an opposite order:
The I/Q data is processed by a digital up-converter (DUC) running on the Red Pitaya’s FPGA.The on-board DAC (125 MS/s sampling frequency, 14-bit resolution) outputs RF signal.An antenna is connected to one of the analog outputs.
The tunable frequency range covers from 0 Hz to 60 MHz.
The I/Q data rate is configurable and five settings are available: 20, 50, 100, 250, 500 and 1250 kSPS.
The basic blocks of the digital down-converters (DDC) and of the digital up-converters (DUC) are shown on the following diagram:
More details can be found on Pavel Demins site.